国際学会発表（査読あり）
| 1 |
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“Improving the Efficiency of Bayesian Optimization Using Robust Scaling Tchebycheff Method in Op-Amp Circuit Design,”
27th IEEE International Conference on Electronics, Circuits & Systems (ICECS 2020),
Marrakech,
Morocco,
(Nov. 2025).
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| 2 |
,
“Accelerating Phase-Lock-Loop Design via Circuit-Level Partitioning and Bayesian Optimization,”
IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2025),
Bandung,
Indonesia,
(Nov. 2025).
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| 3 |
,
“Reducing Simulation Overhead in Analog Circuit Sizing via Stage-Aware Multi Fidelity Optimization,”
IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2025),
Bandung,
Indonesia,
(Nov. 2025).
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| 4 |
,
“Two-Stage Multi-Objective Bayesian Optimization Framework for Analog Circuit Sizing,”
IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2025),
Bandung,
Indonesia,
(Nov. 2025).
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| 5 |
,
“Interpreting and Reducing Variables in Analog Circuit Sizing Models with Explainable AI,,”
NEWCAS,
pp. 177-181,
Paris,
France,
(Jun. 2025).
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| 6 |
,
“Optimal Mapping of Monte Carlo Analysis for Analog Circuit Designing Using Bayesian Neural Networks,”
2025 IEEE 7th International Conference on Artificial Intelligence Circuits and Systems (AICAS),
pp. 70-74,
Bordeaux,
France,
(Apr. 2025).
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| 7 |
,
“Automatic Design of an Analog Integrated Circuits using AI,”
ASP-DAC,
東京,
日本,
(Jan. 2025).
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| 8 |
,
“Op-Amp Sizing with Large Number of Design Variables Using TuRBO,”
Asia Pacific Conference on circuits and Systems (APCCAS),
Taipei,
Taiwan,
(Nov. 2024).
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| 9 |
,
“Control parameters prediction of digital DC-DC converter using A2DoF control by deep learning,”
International Analog VLSI Workshop,
pp. 34-39,
Kuala Lumpur,
Malaysia,
(Oct. 2024).
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| 10 |
,
“Reducing the number of simulations in analog circuit design using SAASBO,”
International Analog VLSI Workshop,
pp. 40-44,
Kuala Lumpur,
Malaysia,
(Oct. 2024).
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| 11 |
,
“Characterization of semantic communication systems considering nonlinear amplifiers,”
International Analog VLSI Workshop,
pp. 44-50,
Kuala Lumpur,
Malaysia,
(Oct. 2024).
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| 12 |
,
“GNN-Curio: Transistor Sizing by Curiosity-Driven Reinforcement Learning with Graph Neural Networks,”
6th International Conference on Circuits and Systems (ICCS 2024),
Chengdu,
China,
(Sep. 2024).
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| 13 |
,
“Comparison of Analog Circuit Sizing Networks and Number of Steps,”
The 9th International Conference on Integrated Circuits Design and Verification (ICDV 2024),
Hanoi,
Vietnam,
(Jun. 2024).
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| 14 |
,
“GNN-Opt: Enhancing Automated Circuit Design Optimization with Graph Neural Networks,”
The 61th Design Automation Conference (DAC 2024),
San Francisco,
U. S. A.,
(Jun. 2024).
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| 15 |
,
“A Method for Opamp Sizing Using Model-Based Reinforcement Learning,”
International Analog VLSI Workshop,
pp. 18-21,
Sinaia,
Romania,
(Oct. 2023).
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| 16 |
,
“ Does AI make analog automation different?,”
IEEE Asian Solid-State Circuits Conference (A-SSCC) Panel Discussion The analog automation: What is the expectation? What is the reality?,
Taipei,
Taiwan,
(Nov. 2022).
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| 17 |
,
“ State-of-the-Art of Automatic Synthesis of Analog Integrated Circuits,”
International Analog VLSI Workshop,
Hiroshima,
Japan,
(Oct. 2022).
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| 18 |
,
“Analog circuit synthesis using multi-label classification,”
International Analog VLSI Workshop,
pp. 118-123,
Online,
(Oct. 2021).
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| 19 |
,
“Filter design for Power Supply Circuits Independent of the Transfer Function of the Control Target Using Deep Learning,”
International Analog VLSI Workshop,
pp. 134-137,
Online,
(Oct. 2021).
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| 20 |
,
“Automatic Synthesis of Operational Amplifier by Learning of Gate Connections using Genetic Algorithm,”
International Analog VLSI Workshop,
pp. 124-127,
Online,
(Oct. 2021).
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